The electrical transmission of fast timing signals introduces timing skew problems resulting from the limited bandwidth associated with the transmission and reception of the electrical signals through conventional electrical cables and transmission lines. One especially deleterious effect of the limited bandwidth is a degradation of fast risetime pulses. As a result, a variation in pulse receiver sensitivity or threshold causes an uncertainty or jitter as to an actual time of the arrival of electrical pulse. If the electrical pulse is being employed as a timing signal in, for example, a high-speed data processing system the presence of pulse jitter is especially detrimental.
FIG. 1 illustrates a simplified diagram of a conventional toggle circuit constructed as a set-reset flip-flop (SR-F/F). The SR-F/F includes two transistors Q.sub.A and Q.sub.B interconnected in a cross-coupled manner as shown. Each transistor is further coupled to a source of operating power (V.sub.dd) through an associated load resistance R.sub.A and R.sub.B. In operation an electrical pulse to INPUT A sets OUTPUT logically HIGH, while an electrical pulse to INPUT B resets the OUTPUT logically LOW. The complementary signal OUTPUT* is LOW when OUTPUT is HIGH and vice versa. One advantage of such a SR-F/F circuit is that the output is always in a known logical state, as is important in the clocking of a computer system. That is, the OUTPUT signal may be employed as a clocking signal for logic circuitry of a computer system.
However, as was previously stated the electrical transmission of fast timing signals introduces timing skew problems resulting from the limited bandwidth associated with the transmission and reception of the electrical signals through conventional electrical cables and transmission lines. That is, if the electrical pulse signals coupled to INPUT A and INPUT B are transmitted through conventional electrical signal transmission means there is a limitation on an upper useable frequency that can be provided to the SR-F/F before the degradation of output pulses and increased output jitter become unacceptable. A problem is created if this upper usable frequency is below a frequency at which it is desired to clock associated logic circuits.
One proposed solution to this problem involves transmitting the input pulses as an optical signal instead of an electrical signal. For example, due to the inherently much wider bandwidth of an optical fiber the transmission of a fast rise time optical pulse through the fiber occurs without significant signal degradation. However, a problem is created when it is required to convert the optical pulse into an electrical signal for interfacing to logic circuits such as the SR-F/F in that optoelectronic circuits generally include electrical switching circuitry coupled to an optical receiver. The receiver typically includes a photosensor followed by several gain stages with output of the gain stages being applied to the associated switching circuitry. A problem with this conventional arrangement relates to the propagation delay between a time light is incident upon the photosensor and a time at which the switching circuit responds by changing state. Another problem relates to temporal jitter resulting from uncertainty in the propagation delay produced by the gain stages proceeding the logic circuitry.
In U.S. Pat. No. 3,686,645, entitled "Charge Storage Flip-Flop" and issued Aug. 22, 1972, Brojdo teaches a semiconductor memory array using a pair of bipolar transistors arranged as a F/F wherein a base of each transistor is connected to a high impedance when a power supply voltage is removed. As the high impedance forces slow decay of charge stored in the transistors, the state of the F/F can be maintained by a pulsed power supply, thereby reducing the average power dissipation of the F/F. Using the photosensitive nature of the transistors, the memory can be written optically by photogenerating charge in the base of one of the transistors, thereby unbalancing the transistors. A laser is employed to address a hologram for providing a desired light pattern for illuminating the memory array. This device specifically uses the low speed nature of the high impedance circuits to integrate the optical signals being applied. Thus, although a F/F circuit configuration is used the application and nature of operation do not address the problem of converting optical pulses into fast rise-time, low jitter electrical logic signals.
In U.S. Pat. No. 4,023,887, entitled "Optical Communication, Switching and Control Apparatus and Systems and Modular Electro-optical Logic Circuits, and Applications thereof" and issued May 17, 1977, Speers discloses optical communication, switching and control apparatus and system, including modular electro-optical logic circuits An optical F--F depicted in FIGS. 38a and 38b and described at Col. 23, lines 3-53 has one optical input and one optical output, and functions basically an optical "repeater" amplifier. It is noted that Speers teaches a binary device wherein the output frequency is one half of the input frequency and individual pulse timing is not preserved. This device is not believed to be suitable for fast rise-time/fall-time, low jitter applications.
The following U.S. Patents are noted of being of general interest. U.S. Pat. No. 4,223,330, entitled "Solid-State Imaging Device", describes a solid-state image pickup device for use in a TV camera and the like. U.S. Pat. No. 4,295,058, entitled "Radiant Energy Activated Semiconductor Switch", describes various power switching circuits using a light sensor such as photodiode coupled to a gate of a depletion-mode FET. U.S. Pat. No. 4,390,790, entitled "Solid State Optically Coupled Electrical Power Switch", relates to optically isolated switching devices such as solid-state relays for power switching or analog switches for signal switching. U.S. Pat. No. 4,521,888, entitled "Semiconductor Device Integrating a Laser and a Transistor", teaches an integrated semiconductor device including a diode laser and a transistor for modulating the laser. U.S Pat. No. 4,739,306, entitled "Calibrated-Weight Balance and an Analog-to-Digital Converter in which the Balance is Employed", discloses a calibrated-weight balance for the construction of very-high-speed analog-to-digital converters (ADC). The circuit includes a multivibrator comprising cross-coupled FETs 15 and 16. However, this Patent does not disclose the provision of optical inputs for driving the multivibrator.
It is thus an object of the invention to provide an optoelectronic pulse converter for converting an optical pulse into an electrical pulse having a fast risetime and a minimum of timing uncertainty.
It is a further object of the invention to provide a timing generation circuit that provides for the transmission of optical pulses of ultrafast risetime through extremely high-bandwidth optical fibers and which further converts these optical pulses into an electrical timing signal having leading and trailing edges exhibiting minimal timing uncertainty.
It is one further object of the invention to provide clock generation circuitry for a high-speed, short cycle time data processor that employs the transmission of optical clock synchronization pulses of ultrafast risetime through extremely high-bandwidth optical fibers and which further converts these optical pulses into an electrical clock signal having a minimal pulse skew.